曙海教育集團論壇FPGA專區(qū)FPGA初中級 → FPGA 時鐘問題


  共有8599人關(guān)注過本帖樹形打印

主題:FPGA 時鐘問題

美女呀,離線,留言給我吧!
wangxinxin
  1樓 個性首頁 | 博客 | 信息 | 搜索 | 郵箱 | 主頁 | UC


加好友 發(fā)短信
等級:青蜂俠 帖子:1393 積分:14038 威望:0 精華:0 注冊:2010-11-12 11:08:23
FPGA 時鐘問題  發(fā)帖心情 Post By:2010-12-19 14:00:46

剛學(xué)不久~

我要做24H製的時鐘~但我一直DEBUG~一直用不出來~

Xilinx ISE 8.2i軟體~

請會的人幫我看一下哪出錯了~謝



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;


---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;


entity CLOCK_00_60 is

    Port ( CLK : in  STD_LOGIC;

           RESET : in  STD_LOGIC;

           ENABLE : out  STD_LOGIC_VECTOR (6 downto 0);

           SEGMENT : out  STD_LOGIC_VECTOR (6 downto 0));

end CLOCK_00_60;


architecture Behavioral of CLOCK_00_60 is

signal SCAN_CLK :STD_LOGIC;

signal COUNT_CLK :STD_LOGIC;

signal DECODE_BCD :STD_LOGIC_VECTOR (3 downto 0);

signal mineable :STD_LOGIC;

signal hreable :STD_LOGIC;

signal POSITION:STD_LOGIC_VECTOR (6 downto 0);

signal DIVIDER:STD_LOGIC_VECTOR (29 downto 1);

signal COUNT_BCD:STD_LOGIC_VECTOR (23 downto 0);


begin

-------------------------------------------------

process (CLK,RESET)

begin

if RESET = '0' then

 DIVIDER <= ( others => '0');

elsif CLK' event and CLK = '1' then

 DIVIDER <= DIVIDER + 1 ;

end if;

end process;

COUNT_CLK<=DIVIDER(24);

SCAN_CLK<=DIVIDER(15);

------------------------------------------------秒

process(RESET,SCAN_CLK)

begin

if RESET = '0' then

 COUNT_BCD <= ( others => '0');

elsif SCAN_CLK' event and SCAN_CLK = '1' then

 if   COUNT_BCD(3 downto 0)= x"9" then

    COUNT_BCD(3 downto 0)<= x"0";

    COUNT_BCD(7 downto 4)<= COUNT_BCD(7 downto 4)+1;

 else

   COUNT_BCD(3 downto 0)<= COUNT_BCD(3 downto 0)+1;

 end if;

end if;

end process;

mineable <= '1' when COUNT_BCD(7 downto 0) = x"59" else '0';

----------------------------------------------------------分


process(RESET,SCAN_CLK)

begin

if RESET = '0' then

 COUNT_BCD <= ( others => '0');

 if mineable = '1' then

elsif SCAN_CLK' event and SCAN_CLK = '1' then

 if   COUNT_BCD(11 downto 8)= x"9" then

    COUNT_BCD(11 downto 8)<= x"0";

    COUNT_BCD(15 downto 12)<= COUNT_BCD(15 downto 12)+1;

 else

   COUNT_BCD(11 downto 8)<= COUNT_BCD(11 downto 8)+1;

 end if;

end if;

end if;

end process;

hreable <= '1' when COUNT_BCD(15 downto 8) = x"59" else '0';

-------------------------------------------------------------時

process(RESET,SCAN_CLK)

begin

if RESET = '0' then

 COUNT_BCD <= ( others => '0');

  if mineable = '1' and hreable = '1' then

elsif SCAN_CLK' event and SCAN_CLK = '1' then

 if   COUNT_BCD(19 downto 16)= x"9" then

    COUNT_BCD(19 downto 16)<= x"0";

    COUNT_BCD(23 downto 20)<= COUNT_BCD(23 downto 20)+1;

  if   COUNT_BCD(19 downto 16)= x"2" then

   COUNT_BCD(23 downto 20)<= x"0";

 else

   COUNT_BCD(19 downto 16)<= COUNT_BCD(19 downto 16)+1;

  end if;

 end if;

  end if;

end if;

end process;



process(RESET,SCAN_CLK)

begin

if RESET = '0' then

 POSITION <= "1111110";

elsif SCAN_CLK' event and SCAN_CLK = '1' then

 POSITION<="111111"&POSITION(0);

end if;

end process;

ENABLE<=POSITION;

-----------------------------------------------------------

process(POSITION,SCAN_CLK)

begin

case POSITION is

 when "1111110" => DECODE_BCD <=COUNT_BCD(3 downto 0);    --秒

 when "1111101" => DECODE_BCD <=COUNT_BCD(7 downto 4);    --秒

 when "1111011" => DECODE_BCD <=COUNT_BCD(11 downto 8);   --分

 when "1110111" => DECODE_BCD <=COUNT_BCD(15 downto 12);   --分

   when "1101111" => DECODE_BCD <=COUNT_BCD(19 downto 16);   --時

   when "1011111" => DECODE_BCD <=COUNT_BCD(23 downto 20);   --時

 when others => null;

end case;

end process;

 

with DECODE_BCD Select

SEGMENT<= "1000000" when X"0",

  "1111001" when X"1",

  "0100100" when X"2",

  "0110000" when X"3",

  "0011001" when X"4",

  "0010010" when X"5",

  "0000010" when X"6",

  "1111000" when X"7",

  "0000000" when X"8",

  "0010000" when X"9",

  "1111111" when others;


end Behavioral;

支持(0中立(0反對(0單帖管理 | 引用 | 回復(fù) 回到頂部
總數(shù) 20 1 2 下一頁

返回版面帖子列表

FPGA 時鐘問題








簽名
主站蜘蛛池模板: 久久国产精品-国产精品| 亚洲国产精品无码专区在线观看| 97色偷偷色噜噜狠狠爱网站| 亚洲激情中文字幕| 日本xxwwxxww在线视频免费| 免费成人在线电影| 久久99久久99精品免视看动漫| 精品国产亚洲第一区二区三区| 国产精品网站在线观看免费传媒 | 国产**a大片毛片| av无码免费永久在线观看| 欧美一区二区三区久久综合| 国产偷亚洲偷欧美偷精品| mm131美女做爽爽爱视频| 最近最新2019中文字幕高清| 午夜福利啪啪片| 亚洲欧美18v中文字幕高清| 成人18视频在线观看| 亚洲人成色7777在线观看不卡| 紧扣的星星完整版免费观看| 国产精品亚洲欧美一区麻豆| 中文字幕亚洲日本岛国片| 欧美成人免费一区二区| 噜噜影院无毒不卡| 你懂的视频在线| 小帅男同志chinesecouple| 亚洲av产在线精品亚洲第一站| 窈窕淑女在线观看免费韩剧| 国产成人福利精品视频| CAOPORN国产精品免费视频| 日本波多野结衣电影| 亚洲最大黄色网站| 综合图区亚洲欧美另类图片 | 国产精品麻豆入口| 中文字幕不卡免费高清视频| 欧美在线看片a免费观看| 午夜爽爽爽男女污污污网站| 国产福利在线导航| 日韩三级在线电影| 亚洲综合伊人久久大杳蕉| 色偷偷人人澡人人爽人人模 |